240-Pin Unbuffered DIMM DDR3 SDRAM
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6.0 DIMM Pin Description
Pin Name Function Pin Name Function
A0 ~ A15 Address input (Multiplexed) ODT0~ODT1 On Die Termination
A10/AP Address Input/Auto pre-charge
CB0~CB7
ECC Data check bits Input/Output
BA0 ~ BA2 Bank Select DQ0~DQ63 Data Input/Output
CK0 ~ CK2, CK0~CK2
Clock input
DQS0~DQS8
Data strobes, negative line
CKE0, CKE1 Clock enable input DM (0~8), Data Masks/Data strobes (Read)
S0, S1
Chip select input DQS0~DQS8 Data Strobes
RAS Row address strobe RFU Reserved for future used
CAS
Column address strobe V
TT
SDRAM I/O termination power supply
WE
Write Enable TEST Memory bus test tool
SCL SPD Clock Input V
DD
Core Power
SDA SPD Data Input/Output V
DDQ
I/O Power
SA0~SA2 SPD Address V
SS
Ground
Par_In
Parity bit for address & Control
bus
V
REF
DQ SDRAM Input/Output Reference Supply
Err_Out
Parity error found in the
Address and Control bus
V
DD
SPD Serial EEPROM Power Supply
RESET
Register and PLL control pin V
REF
CA Command Address Reference Supply
7.0 Address Configuration
Organization Row Address Column Address Bank Address Auto Pre-charge
256Mx8(2Gb) base A0-A14 A0-A9 BA0-BA2 A10/AP
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