204-Pin SODIMM DDR3 SDRAM
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11.4 AC Timing Parameters & Specifications (con’t)
DDR3-1333
Parameter Symbol
min max
Units
Timing of WRA command to Power Down entry
(BL4MRS)
tWRAPDEN WL +2 +WR +1
- nCK
Timing of REF command to Power Down entry tREFPDEN 1
-
Timing of MRS command to Power Down entry tMRSPDEN tMOD(min)
-
ODT Timing
ODT high time without write command or with wirte commandand BC4 ODTH4
4 - nCK
ODT high time with Write command and BL8 ODTH8
6 - nCK
Asynchronous RTT tum-on delay (Power-Down with DLL frozen) tAONPD 1 9
ns
Asynchronous RTT tum-off delay (Power-Down with DLL frozen) tAOFPD 1 9
ns
ODT turn-on tAON -250 250
ps
RTT_NOM and RTT_WR turn-off time from ODTL off reference tAOF 0.3 0.7
tCK(avg)
RTT dynamic change skew tADC 0.3 0.7
tCK(avg)
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining mode is programmed tWLMRD 40 - tCK
DQS/DQS delay after tDQS margining mode is programmed tWLDQSEN 25 - tCK
Setup time for tDQSS latch tWLS 195 -
ps
Hold time of tDQSS latch tWLH 195 -
ps
Write leveling output delay tWLO 0 9
ns
Write leveling output error tWLOE 0 2
ns
