Advantech SOM-Express Design Guide
Chapter 5 Carrier Board Design Guidelines 87
5.12 LPC
SOM-Express provides a LPC interface to some devices like Super I/O , FWH and
others.
5.12.1 Signal Description
Table 5-32 shows SOM-Express LPC signals, including pin number, signals, I/0 and
descriptions.
Table 5-32 LPC signals description
Pin Signal I/O Description
B4,5,6,7 LPC_AD[0:3] O LPC multiplexed address, command and data bus
B3 LPC_FRAME# O LPC frame indicates the start of an LPC cycle
B8,B9 LPC_DRQ[0:1]# O LPC serial DMA request
A50 LPC_SERIRQ O LPC series interrupt
B10 LPC_CLK O LPC clock output – 33MHz nominal
5.12.2 Design Guidelines
5.12.2.1 LPC Design Considerations
Routing requirements for the TPM’s LPC are as follows:
LPC_AD[0:3] are shared with the Firmware Hub (FWH) component and the
Super I/O (SIO) device.
LPC_CLK should be connected to a 33 MHz clock.
LPC_FRAME# (cycle termination) is shared with FWH and the SIO.
LPC_SERIRQ (serialized IRQ) is shared with the SIO.
5.12.2.2 Signal Pull-Up Requirements
The LPC_AD [0:3] signals require pull-up resistors to maintain their state during the
turnaround (TAR) periods of a cycle.
The LPC_DRQ [0:1] signals require pull-ups if they are not connected to a LPC
peripheral device. This will keep them in the inactive state.
See Table 5-33 below for recommended pull-up values. Some host devices will
incorporate these pull-ups internally. Other signals may or may not require pull-up
resistors, depending on the specific system implementation.
Table 5-33 Recommended Pull-Up Values
Signal Name Pull-Up
LAD[3:0] 15k - 100k #
LDRQ[1:0]# 15k - 100k #
5.12.3 Layout Guidelines
5.12.3.1 Placement considerations
Optimum routing can typically be achieved by placing the TPM in proximity to other
LPC peripherals (e.g., firmware hub, super I/O).
The TPM is a security device that should be shielded as much as possible from
physical access. In high-security implementations, a number of mechanisms can be
utilized to detect or prevent physical system intrusion, but such mechanisms are
beyond the scope of this design guide.
