http://www.mcg.mot.com/literature IN-11
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VMEbus requester, DMAC 2-13
VMEbus slave 2-9
VMEbus Slave
Address Modifier Select Register 1 2-36
Address Modifier Select Register 2 2-33
Address Translation Address Offset
Register 1 2-29
Address Translation Address Offset
Register 2 2-31
Address Translation Select Register 1
2-30
Address Translation Select Register 2
2-31
Ending Address Register 1 2-28
Ending Address Register 2 2-29
GCSR Group Address Register 2-47
map decoders 2-26
programming 2-26
Starting Address Register 1 2-28
Starting Address Register 2 2-29
Write Post and Snoop Control Register 1
2-35
Write Post and Snoop Control Register 2
2-32
VMEbus system controller, VMEchip2 2-17
VMEbus timer 2-18
VMEbus to local bus interface 1-9, 2-9
VMEchip2 ASIC 1-2
block diagram 2-5
Board Status/Control Register 2-107
functional blocks 2-4
GCSR programming model 2-101
ID Register 2-105
introduction 2-1
LM/SIG Register 2-105
local BERR* 1-49
memory map, LCSR Summary 2-22
periodic interrupt example B-1
programming model 2-20
Revision Register 2-105
VMEchip2/MC2 chip redundancies 1-5
W
watchdog timer 1-3, 3-8
VMEchip2 2-14, 2-15
Watchdog Timer Control Register 3-43
VMEchip2 2-72
write post 2-34
buffer 2-6, 2-9
bus error interrupter 2-19
register 2-32
timer 2-7
write post enable 2-32, 2-35, 2-39, 2-43,
2-44, 2-50
write posting 2-6, 2-38
definition 2-6
enable 2-51
operations 2-9
write-protect feature 3-2
Z
Z85230 SCC interface 3-6
Z85230 SCC Register addresses 1-37
