2-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
Figure 2-2. MPC8260 Programming ModelÑRegisters
DSISR
SPR 18DSISR
Data Address Register
SPR 19
DAR
SPR 26
SRR0
SPR 27
SRR1
SPRGs
SPR 272SPRG0
SPR 273
SPRG1
SPR 274
SPRG2
SPR 275
SPRG3
Exception Handling Registers
Save and Restore Registers
Instruction BAT
Registers
SPR 528IBAT0U
SPR 529
IBAT0L
SPR 530
IBAT1U
SPR 531
IBAT1L
SPR 532
IBAT2U
SPR 533
IBAT2L
SPR 534
IBAT3U
SPR 535
IBAT3L
Data BAT Registers
SPR 536DBAT0U
SPR 537DBAT0L
SPR 538DBAT1U
SPR 539DBAT1L
SPR 540DBAT2U
SPR 541DBAT2L
SPR 542DBAT3U
SPR 543DBAT3L
Memory Management Registers
Software Table
Search Registers
1
SPR 976DMISS
SPR 977DCMP
SPR 978HASH1
SPR 979HASH2
SPR 980IMISS
SPR 981ICMP
SPR 982RPA
Machine State
Register
MSR
Processor Version
Register
SPR 287PVR
Configuration Registers
Hardware
Implementation
Registers
1
SPR 1008HID0
TBR 268
TBL
TBR 269
TBU
SPR 1
USER MODEL
UISA
Condition Register
GPR0
GPR1
GPR31
General-Purpose
Registers
Floating-Point
Registers
2
XER
XER
SPR 8
Link Register
LR
Time Base Facility
(For Reading)
SUPERVISOR MODELÑOEA
SPR 22
Decrementer
DEC
Time Base Facility
(For Writing)
SPR 284TBL
SPR 285
TBU
SPR 282
External Address
Register (Optional)
EAR
SDR1
SPR 25SDR1
SPR 9
Count Register
CTR
Miscellaneous Registers
SPR 1010IABR
Instruction Address
Breakpoint Register
1
Segment Registers
SR0
SR1
SR15
FPR0
FPR1
FPR31
1
These implementationÐspecific registers may not be supported by other PowerPC processors or processor cores.
SPR 1009HID1
CR
.
USER MODEL
VEA
SPR 1011HID2
2
Although the MPC8260 does not implement an FPU, the LSU can access FPRs if MSR[FP] = 1.
