MOTOROLA
Contents
vii
CONTENTS
Paragraph
Number
Title
Page
Number
2.5.1 PowerPC Exception Model ............................................................................2-22
2.5.2 MPC8260 Implementation-Specific Exception Model..................................2-23
2.5.3 Exception Priorities........................................................................................2-26
2.6 Memory Management ........................................................................................2-26
2.6.1 PowerPC MMU Model ..................................................................................2-27
2.6.2 MPC8260 Implementation-Specific MMU Features .....................................2-28
2.7 Instruction Timing..............................................................................................2-29
2.8 Differences between the MPC8260Õs Core and the PowerPC 603e
Microprocessor...............................................................................................2-30
Chapter 3
Memory Map
Chapter 4
System Interface Unit (SIU)
4.1 System Configuration and Protection ..................................................................4-2
4.1.1 Bus Monitor .....................................................................................................4-3
4.1.2 Timers Clock....................................................................................................4-4
4.1.3 Time Counter (TMCNT)..................................................................................4-4
4.1.4 Periodic Interrupt Timer (PIT) .........................................................................4-5
4.1.5 Software Watchdog Timer ...............................................................................4-6
4.2 Interrupt Controller ..............................................................................................4-7
4.2.1 Interrupt Configuration ....................................................................................4-8
4.2.2 Interrupt Source Priorities ................................................................................4-9
4.2.2.1 SCC, FCC, and MCC Relative Priority .....................................................4-12
4.2.2.2 PIT, TMCNT, and IRQ Relative Priority ..................................................4-12
4.2.2.3 Highest Priority Interrupt ...........................................................................4-13
4.2.3 Masking Interrupt Sources .............................................................................4-13
4.2.4 Interrupt Vector Generation and Calculation.................................................4-14
4.2.4.1 Port C External Interrupts ..........................................................................4-16
4.3 Programming Model ..........................................................................................4-17
4.3.1 Interrupt Controller Registers ........................................................................4-17
4.3.1.1 SIU Interrupt Configuration Register (SICR)............................................4-17
4.3.1.2 SIU Interrupt Priority Register (SIPRR)....................................................4-18
4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L) .................4-19
4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L).....................4-21
4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L) ............................4-22
4.3.1.6 SIU Interrupt Vector Register (SIVEC).....................................................4-23
4.3.1.7 SIU External Interrupt Control Register (SIEXR).....................................4-24
4.3.2 System Configuration and Protection Registers ............................................4-25
4.3.2.1 Bus Configuration Register (BCR) ...........................................................4-25
